`timescale 1ns/1ps
module pulse_test_top;
    reg reset,clk,in;
    wire pulse;

    always # 1 clk = ~clk;
    initial begin
        reset = 0;
        clk = 0;
        in = 0;
        # 2 reset =1;
        # 2 reset =0;
        # 4 in = 1;
        # 5 in = 0; 
        # 5 in = 1;
        # 2 reset =1;
	# 2 reset =0;
        # 3 in = 0;
	# 2 in = 1;
        # 4 $stop;
    end
    pulse_test pt(pulse,in,reset,clk);
	initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, pt);
 	end

endmodule

module pulse_test(pulse,in,reset,clk);
	input in,reset,clk;
    output pulse;
    reg [1:0]state,next;
    parameter RS = 2'b00, S1 = 2'b01,S2 = 2'b10;
    assign pulse = (state == 2'b10)?1:0;
    always @(posedge clk or posedge reset)begin
        if (reset)begin
        	state <= RS;
        end
        else begin
        	state <= next;
        end       
    end
    always @(*)
        case(state)
            RS: next = (in==0)? S1:RS;
            S1: next = (in==1)? S2:S1;
            S2: next = RS;
            default :next = RS;  
        endcase
endmodule

